This application is based upon and claims priority of Japanese Patent Application No. 2001-352203, filed on Nov. 16, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to an association memory which is capable of setting a xe2x80x9cdon""t carexe2x80x9d state to each memory cell thereof and the memory cell used in the association memory.
2. Description of the Related Art
The association memory is a semiconductor device, wherein a search word is inputted and a corresponding storage term is searched to thereby issue its address. There are two known types of the association memory, one being a binary association memory and the other being a ternary association memory. The binary association memory does not have the don""t care function to each storage word. The binary association memory searches for the storage word that completely matches the search word and then outputs its address. The ternary association memory is capable of designating partial bits of the storage word to the don""t care state, so that the designated portion of the storage word is assumed to match irrespective of the search word.
FIG. 13 is a circuit diagram of a memory cell in a conventional binary association memory. The operation of the memory cell will be explained when running the search in the binary association memory. In nodes N1/N2, High level (hereafter referred to as xe2x80x9cHxe2x80x9d)/Low level (hereafter referred to as xe2x80x9cLxe2x80x9d) or L/H is stored. When searching, a word line is set as WL=L and a search data is given to bit lines blz/blx. In a state that the bit lines blz/blx=H/L and the nodes N1/N2=H/L, or the bit lines blz/blx=L/H and the nodes N1/N2=L/H are given (xe2x80x9cMatchxe2x80x9d state), the current does not pass from a match line ML to a reference potential vss (Ground) so that the current potential of the match line ML does not change. In a state that the bit lines blz/blx=L/H and the nodes N1/N2=H/L, or the bit lines blz/blx=H/L and the nodes N1/N2=L/H are given (xe2x80x9cMismatchxe2x80x9d state), the current passes from the match line ML to the reference potential vss (Ground) so that the current potential of the match line ML goes down. The memory cells are so connected to the match line ML as its number corresponds to that of the recorded word. When all the memory cells of the word match, the potential of the match line ML does not change. Even if only one memory cell does not match, the potential of the match line ML decreases. The agreement between the storage word and the search word is searched by judging the potential.
FIG. 14 is a circuit diagram of a memory cell in a conventional ternary association memory. Generally, the ternary association memory is capable of searching a required address with less command numbers, which makes the market needs strong. The operation of the memory cell will be explained when running the search in the ternary association memory. The memory cell comprises two registers to store three states of 0, 1, and don""t care state, and the read/write transistors M01 to M06, and M61 and M64. A storage data for comparing is stored in one resistor M01 and M04, and a don""t-care data to indicate whether it is in a don""t care state or not is stored in the other resistor M61 and M64. When in the don""t care state, the nodes are N3/N4=L/H, and when not in the don""t care state, the nodes are N3/N4=H/L. When in the don""t care state, a transistor M15 is set to be OFF so as to take a match state irrespective of the search data. When not in the don""t care state, the transistor M15 is set to be ON, so as to take the same operation as that in the binary association memory. Accordingly, the memory cell has a disadvantage of becoming larger in size than that of the binary association memory due to the resistors M61 to M64, the read/write transistors M65 and M66 thereof and the transistor M15. Since 2 bits of data are required to be stored in a memory, it is necessary to prepare twice numbers of bit lines blz and blx for the read/write or to take twice times for the read/write, compared to the binary association memory. Further, the ternary association memory requires twice of the total memory capacity compared with the binary association memory, which results in a disadvantage of high possibility of failures to cause a low yield.
Therefore, the ternary association memory compared with the binary association memory having the same storage capacity has disadvantages of cost increase due to increase of the area for the memory cell or decrease of the yield, increase of read/write time or increase of the bus numbers.
The objects of the present invention is reduction of the memory size, improvement of the yield, reduction of the read/write time to the memory cell, and/or reduction of the number of bit lines, in a ternary association memory.
According to an aspect of the present invention, a memory cell of a ternary association memory comprising a register, a transmission circuit, and a match circuit is provided. The register stores the storage data when own memory cell is not in a don""t care state, and stores a don""t care data which indicates whether the adjacent memory cell is in a don""t care state or not, when own memory cell is in a don""t care state. When both of the don""t care data transmitted from one of the adjacent memory cells and the don""t care data stored in its own memory cell indicate a don""t care state, the transmission circuit transmits the don""t care data which indicates that the other of the adjacent memory cells is in the don""t care state to the other of the adjacent memory cells. The match circuit outputs a match data indicating a matching state when a storage data stored in the register and a search data supplied from the outside are matched.
The register stores any of the storage data or the don""t care data, which makes it unnecessary to provide 2 pieces of registers to store both the storage data and the don""t care data. Since one piece of register is necessary to be provided in the memory cell, the total storage capacity of the memory required becomes small, which lowers the possibility of failures so that the yield is increased. In addition, the memory cell and the association memory including thereof can be miniaturized. Further, since the memory cell is required to be provided with only one piece of the registers, execution of the read/write to that one piece of the register can be achieved at a time. In other words, reduction of read/write time to the memory cell and reduction of the number of bit lines can be achieved.